Solid-state light source dimming system and techniques

ABSTRACT

A system and related techniques for dimming a solid-state light source are disclosed. The system may be configured to dim the output of a solid-state emitter via a combination of phase-cut dimming and high-frequency pulse-width modulation (PWM) dimming. To this end, the system may include a digital rectification module configured to generate a rectified DC power and a rectified phase-cut signal based on a phase-cut AC signal received from a phase-cut dimmer. The system further may include a microcontroller unit (MCU) configured to measure the duration of low and high states of the rectified phase-cut signal using zero-crossing digital phase-cut detection and output PWM signal(s) based, at least in part, on those measured values. The rectified DC power and PWM signal(s) may be delivered to a DC-to-DC converter, which may output DC power(s) having an intensity based on the rectified DC power and PWM signal(s), causing receiving emitter(s) to dim.

CROSS-REFERENCE TO RELATED APPLICATIONS AND PRIORITY

This patent application is a continuation of U.S. patent applicationSer. No. 15/669,190 filed on Aug. 4, 2017, the entire disclosure ofwhich is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure generally relates to solid-state lighting (SSL)and more particularly to dimming a solid-state light source.

BACKGROUND

In many conventional lighting systems, phase-cut dimmers have beenimplemented to dim light sources. Generally, phase-cut dimmers cut aportion of each half-cycle of the waveform of an alternating current(AC) signal, which is typically of 50 Hz or 60 Hz line frequency,thereby lowering the effective voltage delivered to the downstream lightsource, lowering the intensity of its output. Phase-cut dimmerstypically modify the sinusoidal waveform of an AC signal at either itsleading edge or its trailing edge. Forward or leading-edge phase-cutcontrol may be provided, for example, by a triode for alternatingcurrent (TRIAC) device. Reverse or trailing-edge phase-cut control maybe found, for example, in an electronic low-voltage (ELV) dimmer device.In either case, the electric power to the light-emitting deviceconnected to the dimmer is reduced, and its light output can be dimmedaccordingly. Pulse-width modulation (PWM) dimming is an alternativeapproach to providing dimming control and is of a higher frequency thantraditional line-frequency phase-cut dimming, making it especiallysuitable for solid-state lighting technologies. Typically, PWM dimmingof solid-state devices is coordinated by an internal processing element.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system configured to control the dimmingof one or more solid-state emitters via a combination of phase-cutdimming and high-frequency pulse-width modulation (PWM) dimming, inaccordance with an embodiment of the present disclosure.

FIG. 2 is a block diagram of a microcontroller unit (MCU) configured inaccordance with an embodiment of the present disclosure.

FIG. 3 illustrates timing diagrams for zero-crossing detection andcounting via a low counter and a high counter in relation to an examplephase-cut alternating current (AC) signal, in accordance with anembodiment of the present disclosure.

FIG. 4 is a flow diagram illustrating a method of half-cycle checkingwhich may be utilized by a half-cycle checking module of an MCU, inaccordance with an embodiment of the present disclosure.

FIG. 5 is a flow diagram illustrating a method of controlling thedimming of a solid-state emitter using phase-cut dimming andhigh-frequency PWM dimming, in accordance with an embodiment of thepresent disclosure.

These and other features of the present embodiments will be understoodbetter by reading the following detailed description, taken togetherwith the figures herein described. The accompanying drawings are notintended to be drawn to scale. In the drawings, each identical or nearlyidentical component that is illustrated in various figures may berepresented by a like numeral. For purposes of clarity, not everycomponent may be labeled in every drawing.

DETAILED DESCRIPTION

A system and related techniques for dimming a solid-state light sourceare disclosed. In accordance with some embodiments, the disclosed systemmay be configured to dim the output of a solid-state emitter via acombination of phase-cut dimming and high-frequency pulse-widthmodulation (PWM) dimming. To this end, the disclosed system may includea digital rectification module configured to generate a rectified DC andphase-cut signal based on a phase-cut AC signal received from anupstream phase-cut dimmer. The system further may include amicrocontroller unit (MCU) configured to measure the duration of low andhigh states of the rectified phase-cut signal using zero-crossingdigital phase-cut detection and output one or more PWM signals based, atleast in part, on those measured values. The rectified DC power and PWMsignal(s) may be delivered to a downstream DC-to-DC converter, which inturn may output DC power(s) having an intensity based on the rectifiedDC power and the PWM signal(s) which causes receiving emitter(s) to dim.Numerous configurations and variations will be apparent in light of thisdisclosure.

General Overview

Many traditional thermal radiation-based, resistive-type lightingsystems utilize line-frequency phase-cut dimming circuitry to dim theoutput of their light sources. Modern smart solid-state lightingelements, however, utilize driving electronics configured to use higherfrequency switching power conversion technology to convert low-frequencyAC line input to a level suitable to drive solid-state emitters.Unfortunately, the phase-cut waveform generated by phase-cut dimmingdevices can fail to provide a consistent current to the solid-stateemitter(s), leading to erratic and unstable flickering of output, amongother performance problems. Therefore, existing phase-cut dimmingdevices are generally considered incompatible with modern smartsolid-state lighting devices, but removal of these legacy dimmingelements from existing infrastructure can be a laborious andcost-prohibitive endeavor. Moreover, existing smart solid-state lightingdevices and systems that utilize pulse-width modulation (PWM) dimmingare often labeled as not to be used or not compatible with suchtraditional phase-cut dimmers. However, given the prevalence ofphase-cut dimmers in existing lighting infrastructure, there is a highlikelihood that, despite these warnings, end-users of newer smartlighting devices may attempt to install wirelessly dimmable smartlighting devices into power sockets wired with incompatible phase-cutdimmers. For end-users unfamiliar with the technical difference betweensmart, wirelessly dimmable and phase-cut dimmable options,disappointment and frustration with the performance of such devices mayresult. Therefore, as newer solid-state lighting technologies continueto grow in popularity and use, there is an increasing need to develop away in which legacy phase-cut dimming circuitry can work in concert withthe additional smart driving electronics associated with solid-stateemitter(s) and related solid-state devices. Thus, and in accordance withsome embodiments of the present disclosure, a system and relatedtechniques for dimming a solid-state light source are disclosed. Inaccordance with some embodiments, the disclosed system may be configuredto dim the output of a solid-state emitter via a combination ofphase-cut dimming and high-frequency PWM dimming. To this end, thedisclosed system may include a digital rectification module configuredto generate a rectified DC power and a rectified phase-cut signal basedon a phase-cut AC signal received from an upstream phase-cut dimmer. Thesystem further may include a microcontroller unit (MCU) configured tomeasure the duration of low and high states of the rectified phase-cutsignal using zero-crossing digital phase-cut detection and output one ormore PWM signals based, at least in part, on those measured values. Therectified DC power and PWM signal(s) may be delivered to a downstreamDC-to-DC converter, which in turn may output DC power(s) having anintensity based on the rectified DC power and the PWM signal(s) whichcauses receiving emitter(s) to dim.

The disclosed system and related techniques may be utilized in any of awide range of example residential, commercial, and other lightingcontexts. In accordance with some embodiments, the disclosed system andrelated techniques may be implemented in any MCU-based smart lightingdevice or system, including, for example, wired smart lighting systemsand stand-alone lighting systems, power line communication (PLC)-basedsmart lighting control systems, and wireless smart lighting systems(e.g., such as Z-wave-based, Zigbee-based, Bluetooth classic-based,Bluetooth smart-based, and Wi-Fi-based smart lighting controls, amongothers), with or without a phase-cut dimmer being present.

In some cases, use of the disclosed system and related techniques mayeliminate or otherwise reduce compatibility problems between existingphase-cut dimmer devices and emerging MCU-based smart lighting devices.In some cases, use of the disclosed system and related techniques mayprovide for a retro-compatible, adaptive, and more flexible dimmingoption for solid-state lighting devices, while also reducing energy costand realizing an improved end-user lighting experience. As describedherein, the MCU of the disclosed system may serve, in a general sense,as a fine dimmer, generating a waveform which may be used to dimemitter(s) digitally with increased precision as compared to the coarsedimming capabilities provided by any upstream phase-cut dimmer. Inaccordance with some embodiments, the disclosed system may employ either(or both) a hardware and a software approach to implementing thedisclosed techniques, and in at least some instances, this approach mayimprove noise tolerance and system robustness as compared to existingapproaches. In accordance with some embodiments, the disclosed systemmay be configured to utilize digital technology to detect phase-cutposition, which then may be used as input to embedded firmware indetermining the digital value of a PWM control signal.

As will be appreciated in light of this disclosure, in using thedisclosed system and related techniques to provide compatibility betweenphase-cut dimmer and digital PWM-based smart lighting devices,additional possibilities may be realized. As a first example, use of thedisclosed techniques may realize one or more benefits with respect tocascade dimming, in accordance with some embodiments. Phase-cut dimmingand smart dimming may work together in a cascade manner to provideultra-fine and ultra-low level deep cascade dimming. This may berealized by using the disclosed MCU as part of a power bleeder. In thedeep dimming state, the additional smart bleeder coordinated by the MCUmay be used.

As a second example, use of the disclosed techniques may realize one ormore benefits with respect to power cycling overriding, in accordancewith some embodiments. Instead of cascade dimming, the phase-cut dimmerand smart digital PWM dimming controller may be configured to overwriteeach other. By implementing the overwriting method(s) inside the smartlighting device, a phase-cut dimmer may overwrite the smart dimmingsetting of the smart lighting device by using power cyclinginterruptions. By using additional power cycling, the smart lightingdevice may be reset back to cascade dimming mode. In some such cases,the actual mode of the smart lighting device and PWM level may bereported to a remote server so that the dimming levels may be trackedand coordinated accordingly. The smart dimming control also mayoverwrite the light output level determined by the phase-cut dimmerposition. This may be implemented by using method(s) to ignore thephase-cut detection result and allow the phase-cut dimmer to deliver itsown desired power to the light emitting diodes (on the condition thatthe phase-cut dimmer still passes sufficient electric energy to thesmart light emitting device).

System Architecture and Operation

FIG. 1 is a block diagram of a system 1000 configured to control thedimming of one or more solid-state emitters 28 via a combination ofphase-cut dimming and high-frequency pulse-width modulation (PWM)dimming, in accordance with an embodiment of the present disclosure. Ascan be seen, system 1000 may include a phase-cut dimmer 20. Phase-cutdimmer 20 may be configured, in accordance with some embodiments, tooutput a phase-cut AC signal based on an AC signal 22 (e.g., such as a50 Hz or 60 Hz AC electrical signal) received from an upstream source.In some embodiments, phase-cut dimmer 20 may be, for example, a linefrequency phase-cut dimmer configured to cut part of each half-cycle ofthe waveform of AC signal 22. In some such cases, phase-cut dimmer 20may be configured to utilize either (or both): (1) leading-edge dimming,by which the leading edge of the waveform of AC signal 22 is cut off; or(2) trailing-edge dimming, by which the trailing edge of the waveform ofAC signal 22 is cut off. In some cases, phase-cut dimmer 20 may includea variable resistor or other means to control cutting of the waveform ofAC signal 22. In some other embodiments, phase-cut dimmer 20 may be, forexample, a triode for alternating current (TRIAC) circuit, asilicon-controlled rectifier circuit (SRC), or an insulated-gate bipolartransistor (IGBT) circuit, among others. In some instances, phase-cutdimmer 20 may be a dimming component of a pre-existing lightinginfrastructure installed for use, for instance, with incandescentlighting or other non-solid-state legacy lamp componentry, as may befound in residential, commercial, or industrial environments, to name afew. In accordance with some embodiments, phase-cut dimmer 20 may beconfigured to utilize cascade dimming in dimming AC signal 22. In somesuch instances, this may provide improved dimming results for emitter(s)28 (discussed below), especially when the output intensity of AC signal22 is relatively low. Other suitable configurations for phase-cut dimmer20 will depend on a given application and will be apparent in light ofthis disclosure. System 1000 also may include a digital rectificationmodule 10 operatively coupled, directly or indirectly, with the outputof upstream phase-cut dimmer 20. Digital rectification module 10 may beconfigured, in accordance with some embodiments, to generate a rectifiedDC power and a rectified phase-cut signal based on the phase-cut ACsignal received from upstream phase-cut dimmer 20. Digital rectificationcircuit 10 may be configured, in accordance with some embodiments, tocondition the phase-cut signal into: (1) a high state (H) correspondingwith the ON phase of upstream phase-cut dimmer 20; and (2) a low state(L) corresponding with the OFF phase of upstream phase-cut dimmer 20.

Digital rectification module 10 may include an input circuit and ACrectifier 12, which may be electrically coupled (e.g., in series) withthe output of upstream phase-cut dimmer 20. Input circuit and ACrectifier 12 may be configured, in accordance with some embodiments, tosuppress surges and isolate internal and external noise from thewaveform of the phase-cut AC signal and generate a rectified DC powerand a rectified phase-cut signal based thereon. As desired for a giventarget application or end-use, input circuit and AC rectifier 12 may beconfigured for either (or both) half-wave rectification or full-waverectification and may include any suitable passive and/or activeelectrical components to those ends, as will be apparent in light ofthis disclosure. As will be appreciated in light of this disclosure,many solid-state emitters and solid-state lighting devices already mayinclude an AC rectifier at the input stage of their electronic drivers,and therefore such pre-existing AC rectifier components optionally maybe utilized, in accordance with some embodiments, in addition to or asan alternative to input circuit and AC rectifier 12. Other suitableconfigurations for input circuit and AC rectifier 12 will depend on agiven application and will be apparent in light of this disclosure.

Digital rectification module 10 also may include an isolation element14, a conditioning diode 16, and a DC isolation diode 18, each of whichmay be configured to provide digital rectification module 10 with agiven desired degree of waveform conditioning. Isolation element 14 maybe, for example, a current-limiting resistor, a coupling capacitor, orboth a resistor and capacitor in serial or parallel configuration, andmay be electrically coupled (e.g., in series) with the output ofupstream input circuit and AC rectifier 12. Conditioning diode 16 maybe, for example, a Zener diode or other voltage-limiting diode and maybe electrically coupled (e.g., in parallel) with the output of upstreamisolation element 14 and the input of downstream microcontroller unit(MCU) 30 (discussed below). DC isolation diode 18 may be configured toisolate the rectified phase-cut signal from interference effects thatotherwise might result from downstream reactive energy storagecomponent(s), such as may be present from downstream DC filter 24 andDC-to-DC convertor 26 (each discussed below), thereby helping tomaintain the integrity of the waveform of the rectified phase-cut signaloutput by upstream input circuit and AC rectifier 12. DC isolation diode18 may be electrically coupled with: (1) the output of upstream inputcircuit and AC rectifier 12; and (2) in parallel with the input ofisolation element 14. Other suitable configurations for isolationelement 14, conditioning diode 16, and DC isolation diode 18 will dependon a given application and will be apparent in light of this disclosure.

System 1000 further may include a DC filter 24 operatively coupled,directly or indirectly, with the output of upstream digitalrectification module 10. DC filter 24 may be configured, in accordancewith some embodiments, to filter inference, noise, and/or signals of agiven frequency from the rectified DC power received from upstreamdigital rectification module 10. To that end, DC filter 24 may includeany one, or combination, of low-pass, high-pass, and band-pass DC filtercircuitry of any suitable configuration, as will be apparent in light ofthis disclosure. Other suitable configurations for DC filter 24 willdepend on a given application and will be apparent in light of thisdisclosure.

System 1000 also may include a DC-to-DC converter 26 operativelycoupled, directly or indirectly, with the output of upstream DC filter24. DC-to-DC converter 26 may be configured, in accordance with someembodiments, to receive: (1) a rectified DC power from upstream DCfilter 24; and (2) one or more high-frequency PWM signals from upstreamMCU 30. DC-to-DC converter 26 may be configured, in accordance with someembodiments, to convert the rectified DC power from a first voltageand/or current level to a second voltage and/or current level based onthe PWM signal(s) and to output DC power(s) to downstream solid-stateemitter(s) 28 (discussed below). The output DC power(s) may be based, atleast in part, on the duty cycle of the PWM signal(s) received from PWMmodule 34 (discussed below) of MCU 30. To these ends, DC-to-DC converter26 may be a linear or switched converter, a step-down (buck) converter,or any other suitable DC-to-DC conversion circuitry, as will be apparentin light of this disclosure. Other suitable configurations for DC-to-DCconverter 26 will depend on a given application and will be apparent inlight of this disclosure.

System 1000 further may include one or more solid-state emitters 28operatively coupled, directly or indirectly, with the output of upstreamDC-to-DC converter 26. Emitter(s) 28 may be configured, in accordancewith some embodiments, to receive the DC power(s) output by upstreamDC-to-DC converter 26 and emit electromagnetic radiation (e.g., light)from any one, or combination, of spectral bands, such as, for example,the visible spectral band, the infrared (IR) spectral band, and theultraviolet (UV) spectral band, among others. A given emitter 28 may bea semiconductor light source, such as a light-emitting diode (LED), anorganic light-emitting diode (OLED), or a polymer light-emitting diode(PLED), among others. As will be appreciated in light of thisdisclosure, emitter(s) 28 may be hosted, for example, by a solid-statelamp, luminaire, or other solid-state light source. Other suitableconfigurations for emitter(s) 28 will be apparent in light of thisdisclosure.

System 1000 further may include a microcontroller unit (MCU) 30operatively coupled, directly or indirectly, with the output of upstreamdigital rectification module 10. FIG. 2 is a block diagram of an MCU 30configured in accordance with an embodiment of the present disclosure.MCU 30 may be configured, in accordance with some embodiments, toprovide processing capabilities for system 1000 and, to that end, mayinclude a processor core, memory, and one or more programmableinput/output ports. In some cases, MCU 30 may include additionalelements, such as, for example, analog-to-digital converter (ADC)componentry and one or more interrupt controls, among others. In someembodiments, MCU 30 may be configured to serve as a current bleeder,improving the load current to an intensity that allows for deeper,low-intensity dimming, particularly when the rectified DC power receivedfrom upstream digital rectification module 10 has a relatively lowintensity. In some embodiments, MCU 30 may be configured to utilizecascade dimming in dimming the rectified DC power, thereby providingimproved dimming results for emitter(s) 28, especially when the outputintensity of the rectified DC power received from upstream digitalrectification module 10 is relatively low.

MCU 30 may include a timer module 32, which may be operatively coupled,directly or indirectly, with the output of upstream digitalrectification module 10. As will be appreciated in light of thisdisclosure, the rectified phase-cut signal received by MCU 30 fromupstream digital rectification module 10 may be of a substantiallysquare waveform, with the high states (H) representing the ON phase ofphase-cut dimmer 20 and the low states (L) representing the OFF phase ofphase-cut dimmer 20. Timer module 32 may be configured, in accordancewith some embodiments, to measure zero-cross behavior of the waveform ofthe rectified phase-cut signal received from upstream digitalrectification module 10. In some embodiments, timer module 32 mayinclude two built-in, consecutive, programmable gate-controlled digitalclock pulse counters—a low counter 33 a and a high counter 33b—configured to measure the zero-crossing behavior of the rectifiedphase-cut signal generated from the original phase-cut AC signalreceived by digital rectification module 10.

FIG. 3 illustrates timing diagrams for zero-crossing detection andcounting via a low counter 33 a and a high counter 33 b in relation toan example phase-cut AC signal, in accordance with an embodiment of thepresent disclosure. As will be appreciated in light of this disclosure,zero-cross detection may include detecting when the voltage of thesubject waveform rises or falls to zero. Timer module 32 may beconfigured, in accordance with some embodiments, to sample the rectifiedphase-cut signal at a sampling frequency designated by MCU 30.

Low counter 33 a may be configured, in accordance with some embodiments,to measure the duration of a low value (L), starting at falling edges ofthe waveform of the rectified phase-cut signal received from upstreamdigital rectification module 10. As generally shown in FIG. 3, theoutput of low counter 33 a may be provided as N1, representing periodsof the OFF phase of phase-cut dimmer 20. During a half-cycle period (orother desired period) of the rectified phase-cut signal received by MCU30, low counter 33 a may count instances where phase-cutting is OFF(corresponding to a low state of the signal), as generally illustratedby N1a and N1b.

High counter 33 b may be configured, in accordance with someembodiments, to measure the duration of a high value (H), starting atrising edges of the waveform of the rectified phase-cut signal receivedfrom upstream digital rectification module 10. As generally shown inFIG. 3, the output of high counter 33 b may be provided as N2,representing periods of the ON phase of phase-cut dimmer 20. During ahalf-cycle period (or other desired period) of the rectified phase-cutsignal received by MCU 30, high counter 33 b may count instances wherephase-cutting is ON (corresponding to a high state of the signal), asgenerally illustrated by N2a and N2b.

Thus, timer module 32 may determine the low value to be the number ofinstances counted by the low counter 33 a and the high value to be thenumber of instances counted by the high counter 33 b. At the end of thepre-determined period, timer module 32 may stop counters 33 a, 33 b andoutput the current low value and high value to PWM module 34 (discussedbelow). Timer module 32 then may reset counters 33 a, 33 b to begincounting at the beginning of a subsequent pre-determined period.Programming of counters 33 a, 33 b may be provided via control bitsetting for MCU 30. Other suitable configurations for timer module 32and its counters 33 a, 33 b will depend on a given application and willbe apparent in light of this disclosure.

MCU 30 also may include a half-cycle checking module 50, which may beoperatively coupled, directly or indirectly, with the output of timermodule 32 and the input of PWM module 34 (discussed below). Half-cyclechecking module 50 may be configured, in accordance with someembodiments, to eliminate (or otherwise reduce) undesired fluctuationsof either (or both) the low value or the high value due to noise orexternal interference, for example. Thus, at least in some instances,half-cycle checking module 50 may serve to improve the noise toleranceand increase the robustness of system 1000. To such end, half-cyclechecking module 50 may utilize a data smoothing routine, in accordancewith some embodiments.

Half-cycle checking module 50 may include a storage module 52. Storagemodule 52 may be configured, in accordance with some embodiments, tostore data pertaining to either (or both): (1) an accepted low valuerelating to the rectified phase-cut signal received from digitalrectification module 10; or (2) an accepted high value relating to therectified phase-cut signal received from digital rectification module10. Storage module 52 further may be configured, in accordance with someembodiments, to store data pertaining to an accepted half-cycle period(or other accepted period) relating to system 1000. In some cases, theaccepted half-cycle period may be, for example, equal to the clockfrequency of MCU 30 divided by twice the frequency of AC signal 22. Itshould be noted, however, that storage module 52 is not limited tostoring only these data, as in accordance with some other embodiments,additional and/or different data may be stored by storage module 52, asdesired for a given target application or end-use. It should be furthernoted that as used herein, a value or period may be considered accepted,for example, if either (or both): (1) it passes the analysis conductedby comparing module 54 (discussed below with respect to FIG. 4); or (2)is designated as accepted by a user or other external source (e.g., viacommunication module 42, discussed below).

Half-cycle checking module 50 also may include a comparing module 54.Comparing module 54 may be configured, in accordance with someembodiments, to compare various values received from timer module 32 andstored by storage module 52. For instance, comparing module 54 maycompare either (or both) the low value or the high value, as receivedfrom timer module 32, against the half-cycle period of the rectifiedphase-cut signal. Comparing module 54 also may compare either (or both)the sum of the low and high values or the difference of the low and highvalues, as received from timer module 32, against the half-cycle periodof the rectified phase-cut signal. In some instances, comparing module54 may compare the low and high values against the half-cycle periodwith a predetermined margin (Δ), as to allow values within that marginto be considered accepted, if desired. In addition, comparing module 54may be configured to compare the low value, as received from timermodule 32, against the accepted low value, as stored by storage module52. Similarly, comparing module 54 may be configured to compare the highvalue, as received from timer module 32, against the accepted highvalue, as stored by storage module 52.

Half-cycle checking module 50 further may include a resetting module 56.Resetting module 56 may be configured, in accordance with someembodiments, to reset either (or both) the low value and the high valueif certain conditions are met, as discussed further below with respectto FIG. 4. If the low value materially exceeds the half-cycle period(optionally with margin), then resetting module 56 may reset the lowvalue. Similarly, if the high value materially exceeds the half-cycleperiod (optionally with margin), then resetting module 56 may reset thehigh value. If comparing module 54 determines any one of the (1) lowvalue, (2) high value, (3) sum of the low and high values, or (4)difference of the low and high values to be accepted, then resettingmodule 56 may not reset that value (or values), and instead thosevalue(s) may be delivered to PWM module 34 (discussed below). If any ofthe (1) low value, (2) high value, (3) sum of the low and high values,or (4) difference of the low and high values is not deemed accepted bycomparing module 54, then resetting module 56 may reset either (or both)the low value or the high value. Resetting module 56 may utilizeaccepted low and high values stored in storage module 52 to resetunaccepted low and high values, respectively.

FIG. 4 is a flow diagram illustrating a method 100 of half-cyclechecking which may be utilized by half-cycle checking module 50 of MCU30, in accordance with an embodiment of the present disclosure. Method100 may begin as in block 102 with determining the half-cycle period(HCCT) and optionally setting the margin (Δ). In accordance with anembodiment, the HCCT may be equal to the clock frequency (f_(Clk)) usedby counters 33 a, 33 b of MCU 30 divided by twice the line frequency(f_(AC)) of AC signal 22. Thus, if AC signal 22 has a line frequency of60 Hz, then the HCCT will be equal to f_(Clk)/120 Hz. Similarly, if ACsignal 22 instead has a line frequency of 50 Hz, then the HCCT will beequal to f_(Clk)/100 Hz. The optional margin (Δ) value may becustomized, as desired for a given target application or end-use.

Method 100 may continue as in block 104 with comparing the low value N1against the HCCT. If the low value N1 is greater than the HCCT, then thelow value N1 may be reset to the last known good value for N1, as inblock 106, and method 100 may proceed as in block 108, discussed below.The last known good value for N1 may represent the minimum accepted lowvalue for N1, which may be customized. If instead the low value N1 isless than or equal to the HCCT, then the low value N1 may not be reset,and method 100 may proceed as in block 108, discussed below.

Method 100 may continue as in block 108 with comparing the high value N2against the HCCT. If the high value N2 is greater than the HCCT, thenthe high value N2 may be reset to the last known good value for N2, asin block 110, and method 100 may proceed as in block 112, discussedbelow. The last known good value for N2 may represent the maximumaccepted high value for N2, which may be customized. If instead the highvalue N2 is less than or equal to the HCCT, then the high value N2 maynot be reset, and method 100 may proceed as in block 112, discussedbelow.

Method 100 may continue as in block 112 with comparing the sum of thelow value N1 and the high value N2 against the sum of the HCCT and themargin. If the sum of the low value N1 and the high value N2 is greaterthan the sum of the HCCT and the margin, then the low value N1 and thehigh value N2 may be reset to the last known good values for N1 and N2,as in block 114, and method 100 may proceed as in block 116, discussedbelow. If instead the sum of the low value N1 and the high value N2 isless than or equal to the sum of the HCCT and the margin, then the lowvalue N1 and the high value N2 may not be reset, and method 100 mayproceed as in block 116.

Method 100 may continue as in block 116 with comparing the sum of thelow value N1 and the high value N2 against the difference of the HCCTand the margin. If the sum of the low value N1 and the high value N2 isless than the difference of the HCCT and the margin, then the low valueN1 and the high value N2 may be reset to the last known good values forN1 and N2, as in block 118, and method 100 may terminate. If instead thesum of the low value N1 and the high value N2 is greater than or equalto the difference of the HCCT and the margin, then the low value N1 andthe high value N2 may not be reset, and method 100 may terminate.

As will be appreciated in light of this disclosure, determining whetherto reset the high value N2 and/or the low value N1 may be accomplishedin any order in method 100, as desired for a given target application orend-use. In accordance with some embodiments, short history data may beused to eliminate (or otherwise reduce) sudden jumping of the low valueN1 and the high value N2 being measured. In some cases, this can be usedin conjunction with one or more suitable data smoothing routines, aswill be apparent in light of this disclosure.

Depending on the results of applying method 100, a low value N1 and ahigh value N2 may be output to PWM module 34 (discussed below). Ifcomparing module 54 determines that any of (1) a low value, (2) a highvalue, (3) a sum of the low and high values, or (4) a difference of thelow and high values materially exceeds the half-cycle period (optionallywith margin), then resetting module 56 may either (or both) replace thelow value with the accepted low value stored by storage module 52 orreplace the high value with the accepted high value stored by storagemodule 52. If resetting module 56 replaces the low value with theaccepted low value, then half-cycle checking module 50 may output theaccepted low value to PWM module 34. Similarly, if resetting module 56replaces the high value with the accepted high value, then half-cyclechecking module 50 may output the accepted high value to PWM module 34.Resetting a high value or low value that materially exceeds theacceptable half-cycle period may allow for the system 1000 to preventundesired increases in measured values due to noise or interference, forexample. In this manner, half-cycle checking module 50 may serve toincrease the robustness of system 1000 and may help to prevent orotherwise reduce the opportunity for undesired changes in the secondwaveform.

In accordance with some embodiments, MCU 30 may be configured for powercycling overriding. For instance, MCU 30 may be configured to powercycle itself entirely or, if desired, a given one of only its variousmodules (e.g., such as PWM module 34, discussed below). To that end, MCU30 may utilize interrupts, counters, or may be power cycled remotely.If, for instance, MCU 30 is triggered to power cycle, then for apredetermined duration during the power cycling, PWM module 34 may notoutput a PWM signal to DC-to-DC converter 26. DC-to-DC converter 26 thenmay output DC power(s) to emitter(s) 28 with an intensity based on apreviously received PWM signal. In another example, if MCU 30 is powercycled such that it may not receive a signal from communication module42, then PWM module 34 may output a PWM signal without considering anysignal transmitted by communication module 42 (discussed below). Powercycling overriding of MCU 30 may allow for a PWM waveform to begenerated based on the low and high values measured by timer module 32or, in some cases, the output from half-cycle checking module 50.

As previously noted, MCU 30 may include a PWM module 34, which may beoperatively coupled, directly or indirectly, with upstream half-cyclechecking module 50 and downstream DC-to-DC converter 26. PWM module 34may be configured, in accordance with some embodiments, to receive fromupstream half-cycle checking module 50 any one (or combination) of thelow value, the high value, the accepted low value, and the accepted highvalue. From these received value(s), which are based on the rectifiedphase-cut signal received by MCU 30 from digital rectification module10, PWM module 34 may generate one or more high-frequency PWM signals,which may be provided, directly or indirectly, to DC-to-DC converter 26.A given PWM signal output by PWM module 34 may have a duty cycle based,at least in part, on the value(s) received from half-cycle checkingmodule 50 and may be indicative of the desired output DC power(s) ofDC-to-DC converter 26, serving to limit the DC voltage(s) and/orcurrent(s) received by downstream emitter(s) 28. In accordance with someembodiments, PWM module 34 may generate a PWM signal of a waveformincluding about a 50% duty cycle based on the value(s) received fromhalf-cycle checking module 50. In accordance with some embodiments, PWMmodule 34 may be configured to adjust its high-frequency PWM signaloutput as it receives value(s) from half-cycle checking module 50,changing at a frequency less than or equal to the clock frequency of MCU30.

In accordance with some other embodiments, PWM module 34 also may beoperatively coupled, directly or in directly, with communication module42 (discussed below). In this manner, PWM module 34 may receive acontrol signal or other signal from a remote source via communicationmodule 42 and, in response to that signal, adjust its PWM signal output.In some cases, PWM module 34 may generate a PWM control signal basedsolely on input from a remote source (e.g., such as may be received viacommunication module 42), provided that the PWM signal represents anintensity less than a maximum intensity of the rectified DC power.Notwithstanding any communication with communication module 42, if thevalue(s) received by PWM module 34 from half-cycle checking module 50are equal, then that condition may represent the state where theintensity of emitter(s) 28 is about half (e.g., about 50%) of themaximum emitter intensity possible. If, however, PWM module 34 insteadreceives a control signal from communication module 42 that represents adesired dimming intensity, for example, of 30% of the maximum intensityof the rectified DC power, provided that that waveform is of sufficientpower to achieve 30% maximum intensity, then PWM module 34 may output aPWM signal representing an intensity of about 30% of the maximumintensity of the rectified DC power. If, however, the rectified DC poweris not of sufficient power to support the desired 30% of maximumintensity, then emitter(s) 28 may emit light with an intensityrepresenting the intensity of that rectified DC power. Other suitableconfigurations for PWM module 34 will depend on a given application andwill be apparent in light of this disclosure.

As previously noted, system 1000 optionally may include a communicationmodule 42, which may be operatively coupled, directly or indirectly,with MCU 30. Communication module 42 may be configured, in accordancewith some embodiments, to enable communication between MCU 30 and one ormore remote entities external to system 1000. In some instances,communication module 42 may be configured to communicate with anexternal network, server, database, or computing device, which maytransmit data to and/or receive data from MCU 30 (or other portion ofsystem 1000). To such ends, communication module 42 may be configured asa transmitter, a receiver, or both (i.e., a transceiver). Communicationmodule 42 may be configured for wired or wireless communication (orboth) utilizing any one, or combination, of suitable means, such asUniversal Serial Bus (USB), Ethernet, FireWire, Wi-Fi, Bluetooth, orZigBee, among others. In some cases, communication module 42 may beseparate and distinct from MCU 30 (e.g., as generally shown in FIG. 1),though in some other cases, communication module 42 may be a componentof or otherwise integrated with MCU 30.

In accordance with some embodiments, MCU 30 may be configured to outputPWM signal(s) to emitter(s) 28 based, at least in part, on inputreceived from a remote source, such as a control interface communicatingthrough communication module 42. The control interface may be physical,virtual, or a combination thereof and may be configured to communicatewith MCU 30 (via intervening communication module 42), which in turninterprets input received from the control interface and distributesdesired PWM signal(s) to DC-to-DC converter 26, which in turn suppliesDC power to emitter(s) 28. In accordance with some embodiments,communication module 42 may be used in remotely, digitally controllingthe PWM signal waveform generated by PWM module 34. For instance, aremote source may output a control signal which is relayed bycommunication module 42 to MCU 30, and MCU 30 in turn may instruct itsPWM module 34 to output a PWM signal based, at least in part, on dataprovided in that control signal received from communication module 42.Other suitable configurations for communication module 42 will depend ona given application and will be apparent in light of this disclosure.

In accordance with some embodiments, communication module 42 may relay acontrol signal to MCU 30 to cause PWM module 34 to output a PWM signalhaving a waveform representing a function of the waveform of therectified phase-cut signal received from digital rectification module10. For example, if (1) communication module 42 transmits a signal toPWM module 34 that indicates a desire to output a PWM signal having awaveform with an intensity that is about 50% less than the intensity ofthe rectified DC power, and (2) timer module 32 measures low and highvalues of the rectified phase-cut signal waveform that represent about40% of the maximum intensity possible, then (3) PWM module 34 may outputa PWM signal having a waveform representing an intensity of about 20% ofthe maximum intensity, which substantially equates to 50% less than the40% of the maximum intensity of the rectified DC power. Continuing thepresent example, if (1) phase-cut dimmer 20 and digital rectificationmodule 10 subsequently change the waveform of the rectified phase-cutsignal to 30% of the maximum intensity possible, and (2) timer module 32measures low and high values of the rectified phase-cut signal waveformthat represent about 30% of the maximum intensity possible, then (3) PWMmodule 34 may output a PWM signal having a waveform representing anintensity of about 15% of the maximum intensity, which substantiallyequates to 50% less than the 30% of the maximum intensity of therectified DC power.

As previously noted, in some instances, communication module 42 may beconfigured to communicate with a remote server. In this manner, MCU 30may transmit data pertaining to its present mode of operation to theremote server so that the present dimming levels and settings of system1000 may be recorded and coordinated by the remote server. In somecases, data pertaining to the characteristics of the PWM signal(s)output by PWM module 34 may be transmitted by communication module 42 tothe remote server, where they may be stored.

As previously explained, counters 33 a, 33 b may be configured tomeasure the zero-cross behavior of the rectified phase-cut signalgenerated by digital rectification module 10 from the phase-cut ACsignal output by phase-cut dimmer 20. Counter 33 a may measure theduration of the low state and report its results as N1, whichcorresponds with the OFF phase of the phase-cut. Counter 33 b maymeasure the duration of the high state and report its results as N2,which corresponds with the ON phase of the phase-cut. In accordance withsome embodiments, the angular phase position of phase-cut dimmer 20 canbe calculated via the following relationship:

${{Angular}\mspace{14mu}{PhaseCut}\mspace{14mu}{Position}} = {\left( \frac{N\; 1}{\left( {{N\; 1} + {N\; 2}} \right)} \right) \times 180.}$

Because N1 and N2 are both in digital format, the digital result may beused directly by PWM module 34 in generating one or more PWM signals, inaccordance with some embodiments. However, with this approach todigitally calculating angular phase-cut position, there are twodegenerated states: (1) when N1 is virtually zero (e.g., the full brightstate); and (2) when N2 is virtually zero (e.g., the full dim state).When N1 is virtually zero, N2 mathematically becomes perpetual, thoughthe perpetual state of N2 will not actually occur because thezero-crossing detection output will stop the N2 counter after thatactive half-cycle is over. For the same reason, the second half-cyclefollowing that active N2 half-cycle can be mistakenly treated as N1, andthe degenerated real no-phase-cut can be interpreted erroneously as a50% (e.g., 90°) phase-cut. The full dim state (where N2 is virtuallyzero) can have consequences like those of the full bright state,discussed above. Because of the sequential nature of N1 and N2, it maynot be so straightforward for MCU 30 to tell which one is which whenimplementing the described zero-crossing approach. If not properlyaddressed, the brighten and dim functions could be reversed, and system1000 could become unstable. Thus, to address these non-trivialcomplications, a different approach may be employed, measuring only thehigh state H via high counter 33 b first. Because the sum of the lowstate L and the high state H is the half-period of the AC signal 22, onecan obtain the angular phase-cut position by calculating

${\left( \frac{\left( {T_{A\; C} - T_{H}} \right)}{T_{A\; C}} \right) \times 180},$

where T_(AC) is either 20 msec (e.g., if the frequency of AC signal 22is 50 Hz) or 16.66 msec (e.g., if the frequency of AC signal 22 is 60Hz), and T_(H) relates to the high state H. T_(AC) may be measureddirectly by counting the time interval between the same edges (i.e.,either rising edges or falling edges) of the rectified phase-cut signaloutput of digital rectifier module 10. Because the falling and risingedges are well-processed, there may be no need to use consecutivecontrol. In this manner, the zero-phase degenerate and N1 and N2confusions, each discussed above, may be eliminated, in accordance withsome embodiments.

In an example case of a smart lighting platform utilizing a CC2530Second Generation System-on-Chip (SoC) device, available from TexasInstruments, Inc., the Timer 4 channel 0 was utilized to measure H and(L+H), and the digital rectifier output was wired to P2.0(PERCFG.T4CFG<−alt.2). The Timer 4 was setup for edge-trigger captureinterrupt mode, and the counter was reset to zero at the rising edge.With this setup, once a digital level change edge was detected, theinterrupt routine checked the internal register that contains a snapshotof the respective timer and counter registers at the moment of thetrigger. By subtracting successive trigger timestamps, the duration of Hand the period (e.g., the sum of L and H) may be calculated accordingly.The results may be further checked against the half-cycle period and thelast known good values for data integrity and consistency.

Methodology

FIG. 5 is a flow diagram illustrating a method 200 of controlling thedimming of a solid-state emitter using phase-cut dimming andhigh-frequency PWM dimming, in accordance with an embodiment of thepresent disclosure. Method 200 may begin as in block 202 with rectifyinga phase-cut AC signal into a rectified phase-cut signal, and optionallya rectified DC power. In some cases, the phase-cut AC signal may berectified, more generally, into at least one of a rectified phase-cutsignal and a rectified DC power. In accordance with some embodiments,rectification may be provided by a digital rectification module 10, asdiscussed above.

Method 200 may continue as in block 204 with measuring a duration ofeach of a low state and a high state of the rectified phase-cut signaland outputting corresponding low and high values, respectively. Inaccordance with some embodiments, such measuring may be provided by atimer module 32 (e.g., having a low counter 33 a and a high counter 33b), as discussed above. The measuring may involve zero-crossingdetection, where the low value is measured starting at a falling edge ofthe rectified phase-cut signal and the high value is measured startingat a rising edge of the rectified phase-cut signal.

Method 200 may continue as in block 206 with generating a PWM signalbased on each of the low value and the high value of the rectifiedphase-cut signal. In accordance with some embodiments, such generatingmay be provided by a PWM module 34, as discussed above. Method 200 maycontinue as in block 208 with generating a DC power(s) based on therectified DC power and the PWM signal and supplying the DC power(s) tosolid-state emitter(s). In accordance with some embodiments, thegenerating may be provided by a DC-to-DC converter 26, as discussedabove. One or more emitters 28, as discussed above, may receive the DCpower(s) and emit light in response.

In accordance with some embodiments, the PWM signal generated in block206 may be modified based on input received from an external source. Forinstance, as discussed above, a communication module 42 may relayinformation to MCU 30, which instructs PWM module 34 to adjust its PWMsignal output. In some instances, the PWM signal may be modified as afunction of the duration of the rectified phase-cut signal generated inblock 202. In accordance with some embodiments, in generating the PWMsignal in block 206, method 200 may include modifying the PWM signalbased on input received by communication module 42 when the output DCpower(s) corresponding to the rectified phase-cut signal are greaterthan the output DC power(s) designated in the signal received bycommunication module 42.

In accordance with some embodiments, after measuring the duration of thelow and high values in block 204, method 200 may include storing ahalf-cycle period and an accepted high value and an accepted low valueof the rectified phase-cut signal. In generating the PWM signal in block206, method 200 may include comparing the accepted high value and theaccepted low value against the half-cycle period of the rectifiedphase-cut signal. In generating the PWM signal in block 206, method 200may include resetting the low and high values utilizing the accepted lowand high values, respectively, when a sum or a difference of theaccepted low and high values exceeds the half-cycle period.

Numerous embodiments will be apparent in light of this disclosure. Oneexample embodiment provides a system for controlling the dimming of asolid-state light source. The system includes a digital rectificationmodule configured to rectify a phase-cut alternating current (AC) signalinto: a rectified direct current (DC) power; and a rectified phase-cutsignal. The system further includes a microcontroller configured toreceive the rectified phase-cut signal. The microcontroller includes atimer module configured to: measure, within a given period, a durationof a low state of the rectified phase-cut signal and output a low valuebased thereon; and measure, within the given period, a duration of ahigh state of the rectified phase-cut signal and output a high valuebased thereon. The microcontroller further includes a PWM moduleconfigured to generate a pulse-width modulation (PWM) signal based on atleast one of the low value and the high value. In some cases, thedigital rectification module includes an input circuit and AC rectifierconfigured to receive the phase-cut AC signal from a phase-cut dimmer.In some such cases, the digital rectification module further includes:an isolation element electrically coupled in series with the inputcircuit and AC rectifier; a conditioning diode electrically coupled inseries with the isolation element; and an isolation diode electricallycoupled in series with the input circuit and AC rectifier and inparallel with the isolation element. In some instances, the timer moduleis configured to utilize zero-crossing detection in measuring each ofthe duration of the low state and the duration of the high state of therectified phase-cut signal. In some such instances: the duration of thelow state is measured starting at a falling edge of the rectifiedphase-cut signal; and the duration of the high state is measuredstarting at a rising edge of the rectified phase-cut signal. In somecases: the microcontroller further includes a half-cycle checking moduleconfigured to compare the low value and the high value against anaccepted low value and an accepted high value, respectively; and the PWMmodule is configured to generate the PWM signal based on at least one ofthe low value, the high value, the accepted low value, and the acceptedhigh value. In some such cases, the half-cycle checking module includesa storage module configured to store the accepted low value and theaccepted high value of the rectified phase-cut signal. The half-cyclechecking module also includes a comparing module configured to: comparethe low value against a half-cycle period of the rectified phase-cutsignal; and compare the high value against the half-cycle period of therectified phase-cut signal. The half-cycle checking module furtherincludes a resetting module configured to: reset the low value with theaccepted low value if the low value exceeds the accepted low value; andreset the high value with the accepted high value if the high valueexceeds the accepted high value. In some instances, the system furtherincludes a communication module configured to communicate with themicrocontroller and a remote device external to the system, wherein thePWM module is further configured to generate the PWM signal based oninput received via the communication module. In some cases, the systemfurther includes a DC filter configured to filter the rectified DC poweroutput by the digital rectification module. In some instances, thesystem further includes a DC-to-DC converter configured to: receive therectified DC power from the digital rectification module; receive thePWM signal from the PWM module; and generate at least one DC power basedon the rectified DC power and the PWM signal and supply the at least oneDC power to the solid-state light source.

Another example embodiment provides a method of controlling light outputof a solid-state light source. The method includes rectifying aphase-cut alternating current (AC) signal into: a rectified DC power;and a rectified phase-cut signal. The method also includes measuring aduration of each of a low state and a high state of the rectifiedphase-cut signal and outputting a corresponding low value and highvalue, respectively. The method also includes generating a pulse-widthmodulation (PWM) signal based on each of the low value and the highvalue of the rectified phase-cut signal. The method also includesgenerating at least one direct current (DC) power based on the rectifiedDC power and the PWM signal and supplying the at least one DC power tothe solid-state light source. In some cases, rectifying the phase-cut ACsignal is performed via a digital rectification module including aninput circuit and AC rectifier configured to receive the phase-cut ACsignal from a phase-cut dimmer. In some such cases, the digitalrectification module further includes: an isolation element electricallycoupled in series with the input circuit and AC rectifier; aconditioning diode electrically coupled in series with the isolationelement; and an isolation diode electrically coupled in series with theinput circuit and AC rectifier and in parallel with the isolationelement. In some instances, measuring the duration of each of the lowstate and the high state of the rectified phase-cut signal andoutputting the corresponding low value and high value are performed viaa microcontroller configured to receive the rectified phase-cut signal.The microcontroller includes a timer module configured to: measure,within a given period, the duration of the low state and output the lowvalue based thereon; and measure, within the given period, the durationof the high state and output the high value based thereon. Themicrocontroller also includes a half-cycle checking module configured tocompare the low value and the high value against an accepted low valueand an accepted high value, respectively. In some such instances,generating the PWM signal based on each of the low value and the highvalue of the rectified phase-cut signal is performed via themicrocontroller, wherein the microcontroller further includes a PWMmodule configured to generate the PWM signal based on at least one ofthe low value, the high value, the accepted low value, and the acceptedhigh value. In some cases, the timer module is configured to utilizezero-crossing detection in measuring each of the duration of the lowstate and the duration of the high state of the rectified phase-cutsignal. In some such cases, the duration of the low state is measuredstarting at a falling edge of the rectified phase-cut signal; and theduration of the high state is measured starting at a rising edge of therectified phase-cut signal. In some instances, the half-cycle checkingmodule includes a storage module configured to store the accepted lowvalue and the accepted high value of the rectified phase-cut signal. Thehalf-cycle checking module also includes a comparing module configuredto: compare the low value against a half-cycle period of the rectifiedphase-cut signal; and compare the high value against the half-cycleperiod of the rectified phase-cut signal. The half-cycle checking modulefurther includes a resetting module configured to: reset the low valuewith the accepted low value if the low value exceeds the accepted lowvalue; and reset the high value with the accepted high value if the highvalue exceeds the accepted high value. In some cases, generating the PWMsignal is further based on input received from a remote source via acommunication module configured to communicate with the microcontroller.In some instances, the method further includes filtering, via a DCfilter, the rectified DC power output by the digital rectificationmodule. In some cases, generating the at least one DC power based on therectified DC power and the PWM signal and supplying the at least one ofDC power to the solid-state light source are performed via a DC-to-DCconverter.

The foregoing description of example embodiments has been presented forthe purposes of illustration and description. It is not intended to beexhaustive or to limit the present disclosure to the precise formsdisclosed. Many modifications and variations are possible in light ofthis disclosure. It is intended that the scope of the present disclosurebe limited not by this detailed description, but rather by the claimsappended hereto. Future-filed applications claiming priority to thisapplication may claim the disclosed subject matter in a different mannerand generally may include any set of one or more limitations asvariously disclosed or otherwise demonstrated herein.

What is claimed is:
 1. A system for controlling the dimming of asolid-state light source, the system comprising: a digital rectificationmodule configured to rectify a phase-cut alternating current (AC) signalinto: a rectified direct current (DC) power; and a rectified phase-cutsignal; and a microcontroller configured to receive the rectifiedphase-cut signal, wherein the microcontroller is configured to: measure,within a given period, a duration of a low state of the rectifiedphase-cut signal and output a low value based thereon; measure, withinthe given period, a duration of a high state of the rectified phase-cutsignal and output a high value based thereon; and generate a signalbased on at least one of the low value and the high value.
 2. The systemof claim 1, wherein the signal is a pulse-width modulation (PWM) signal.3. The system of claim 2, wherein the microcontroller is furtherconfigured to: compare the low value and the high value against anaccepted low value and an accepted high value, respectively; andgenerate the PWM signal based on at least one of the low value, the highvalue, the accepted low value, and the accepted high value.
 4. Thesystem of claim 3, wherein the microcontroller is further configured to:store the accepted low value and the accepted high value of therectified phase-cut signal; compare the low value against a half-cycleperiod of the rectified phase-cut signal; compare the high value againstthe half-cycle period of the rectified phase-cut signal; reset the lowvalue with the accepted low value if the low value exceeds the acceptedlow value; and reset the high value with the accepted high value if thehigh value exceeds the accepted high value.
 5. The system of claim 2,wherein the microcontroller is further configured to communicate with aremote device external to the system, wherein the microcontroller isfurther configured to generate the PWM signal based on input receivedvia the remote device.
 6. The system of claim 1, wherein the digitalrectification module comprises an input circuit and AC rectifierconfigured to receive the phase-cut AC signal from a phase-cut dimmer.7. The system of claim 6, wherein the digital rectification modulefurther comprises: an isolation element electrically coupled in serieswith the input circuit and AC rectifier; a conditioning diodeelectrically coupled in series with the isolation element; and anisolation diode electrically coupled in series with the input circuitand AC rectifier and in parallel with the isolation element.
 8. Thesystem of claim 1, wherein the microcontroller is configured to utilizezero-crossing detection in measuring each of the duration of the lowstate and the duration of the high state of the rectified phase-cutsignal.
 9. The system of claim 1, wherein: the duration of the low stateis measured starting at a falling edge of the rectified phase-cutsignal; and the duration of the high state is measured starting at arising edge of the rectified phase-cut signal.
 10. The system of claim1, further comprising a DC-to-DC converter configured to: receive therectified DC power from the digital rectification module; receive thesignal from the microcontroller; and generate at least one DC powerbased on the rectified DC power and the signal and supply the at leastone DC power to the solid-state light source.
 11. A method ofcontrolling light output of a solid-state light source, the methodcomprising: rectifying a phase-cut alternating current (AC) signal into:a rectified DC power; and a rectified phase-cut signal; measuring aduration of each of a low state and a high state of the rectifiedphase-cut signal and outputting a corresponding low value and highvalue, respectively; generating a pulse-width modulation (PWM) signalbased on each of the low value and the high value of the rectifiedphase-cut signal; and generating at least one direct current (DC) powerbased on the rectified DC power and the PWM signal and supplying the atleast one DC power to the solid-state light source.
 12. The method ofclaim 11, wherein rectifying the phase-cut AC signal is performed via adigital rectification module comprising an input circuit and ACrectifier configured to receive the phase-cut AC signal from a phase-cutdimmer.
 13. The method of claim 12, wherein the digital rectificationmodule further comprises: an isolation element electrically coupled inseries with the input circuit and AC rectifier; a conditioning diodeelectrically coupled in series with the isolation element; and anisolation diode electrically coupled in series with the input circuitand AC rectifier and in parallel with the isolation element.
 14. Themethod of claim 11, wherein measuring the duration of each of the lowstate and the high state of the rectified phase-cut signal andoutputting the corresponding low value and high value are performed viaa microcontroller configured to receive the rectified phase-cut signal,wherein the microcontroller comprises: a timer module configured to:measure, within a given period, the duration of the low state and outputthe low value based thereon; and measure, within the given period, theduration of the high state and output the high value based thereon; anda half-cycle checking module configured to compare the low value and thehigh value against an accepted low value and an accepted high value,respectively.
 15. The method of claim 14, wherein generating the PWMsignal based on each of the low value and the high value of therectified phase-cut signal is performed via the microcontroller, whereinthe microcontroller further comprises: a PWM module configured togenerate the PWM signal based on at least one of the low value, the highvalue, the accepted low value, and the accepted high value.
 16. Themethod of claim 14, wherein the timer module is configured to utilizezero-crossing detection in measuring each of the duration of the lowstate and the duration of the high state of the rectified phase-cutsignal.
 17. The method of claim 14, wherein the half-cycle checkingmodule comprises: a storage module configured to store the accepted lowvalue and the accepted high value of the rectified phase-cut signal; acomparing module configured to: compare the low value against ahalf-cycle period of the rectified phase-cut signal; and compare thehigh value against the half-cycle period of the rectified phase-cutsignal; and a resetting module configured to: reset the low value withthe accepted low value if the low value exceeds the accepted low value;and reset the high value with the accepted high value if the high valueexceeds the accepted high value.
 18. The method of claim 11, wherein:the duration of the low state is measured starting at a falling edge ofthe rectified phase-cut signal; and the duration of the high state ismeasured starting at a rising edge of the rectified phase-cut signal.19. A system for controlling the dimming of a solid-state light source,the system comprising: a digital rectification module comprising: aninput circuit; an AC rectifier configured to receive the phase-cut ACsignal from a phase-cut dimmer; an isolation element electricallycoupled in series with the input circuit and AC rectifier; aconditioning diode electrically coupled in series with the isolationelement; and an isolation diode electrically coupled in series with theinput circuit and AC rectifier and in parallel with the isolationelement, wherein the digital rectification module is configured torectify a phase-cut alternating current (AC) signal into: a rectifieddirect current (DC) power; and a rectified phase-cut signal; and amicrocontroller configured to receive the rectified phase-cut signal,wherein the microcontroller is configured to: measure a duration of astate of the rectified phase-cut signal and output a value thereon; andgenerate a signal based on the value.
 20. A method of controlling lightoutput of a solid-state light source, the method comprising: rectifyinga phase-cut alternating current (AC) signal into: a rectified DC power;and a rectified phase-cut signal, wherein rectifying the phase-cut ACsignal is performed via a digital rectification module comprising: aninput circuit, an AC rectifier configured to receive the phase-cut ACsignal from a phase-cut dimmer, an isolation element electricallycoupled in series with the input circuit and AC rectifier, aconditioning diode electrically coupled in series with the isolationelement, and an isolation diode electrically coupled in series;measuring a duration of at least one state of the rectified phase-cutsignal and outputting a value; generating a signal based on the value ofthe rectified phase-cut signal; and generating at least one directcurrent (DC) power based on the rectified DC power and the signal.